Non-volatile, re-programmable memory devices such as flash memory are highly desirable and have many applications from storing a computer system's BIOS to functioning as a memory for devices such as digital cameras. Typically, such memory devices may be reprogrammed hundreds of thousands of times and may be programmed or erased in blocks of, for example, hundreds or thousands of bits. Such devices may operate by storing a charge in a memory cell. For example, a typical flash memory cell may be programmed to hold a charge in a floating gate region of a transistor.
A flash memory cell can be a field effect transistor (FET) that includes a select gate, a floating gate, a drain, and a source. The select gate will also be referred to throughout this description as “the gate.” A memory cell can be read by grounding the source, and applying a voltage to a bitline connected with the drain. By applying a voltage to the wordline connected to the select gate, the cell can be switched on and off.
Programming a memory cell is achieved by trapping excess electrons in the floating gate to increase the threshold voltage. This reduces the current conducted by the memory cell when the select voltage is applied to the select gate. The memory cell is programmed to a desired level if the memory cell current is less than a reference current while the select voltage is applied to the select gate. The memory cell is erased when the memory cell current is greater than the reference current while the select voltage is applied.
Memory cells with only two programmable states contain only a single bit of information, such as a “0” or a “1”. A multi-level cell (“MLC”) can be programmed with more than one level. For example, a memory cell can be programmed to have one of four different threshold voltages. Each threshold voltage level is mapped to corresponding bits of information. Thus, a multi-level cell is programmed with one of four threshold voltage levels that correspond to binary “00”, “01”, “10”, and “11”. Unfortunately, a shift in the threshold voltage after programming can cause a data misread.
Two of the primary causes of threshold voltage shift are the “data retention” effect and the “read disturb” effect. The “data retention” effect is a shift in threshold voltage that results from the normal passage of time. This shift in the threshold voltage toward the erase state (e.g., lowest threshold voltage). The “read disturb” effect is a shift in the threshold voltage that results from reading the memory cell. For the read disturb effect to be appreciable, typically many reads must occur. The read disturb effect is away from the erase state (e.g., increases the threshold voltage). When the threshold voltage level shifts too far in either direction, it will be interpreted as representing the next higher or lower threshold voltage level and thus the data will be misread. To prevent such misreads, the memory cells can be programmed in a narrow distribution, which increases the margin between the states.
Prior art FIG. 1 shows a representation of a four-level multilevel cell program voltage diagram 100. The program voltage distribution (“distribution”) of the four levels are shown between lines 102 and 104, 106 and 108, lines 110 and 112, and above line 114, respectively. The programming distribution for the lowest level is about 2.5V, distribution of middle two levels are about 500 mV, and the distribution of the highest level is about IV. A four-level multilevel memory cell can be programmed with any one of these voltage levels. Because the cell can store one of four binary values, it can store two bits of information. The data margin (“margin”), also called a guard band, is the voltage levels between distributions that is not normally used. The margins are shown in prior art FIG. 1 between lines 104 and 106; lines 108 and 110; and lines 112 and 114. For example, the data margin can be about 700 mV to IV.
Prior art FIG. 2 is a graph 200 illustrating the effect of the phenomena called “read disturb.” Read disturb occurs after the cell has been read many times without being reprogrammed. The programming distributions are shifted to the right, which represents a positive voltage shift. Distributions 230, 232, 234, and 236 represent the distributions 220, 222, 224, and 226 after they have been affected by the read disturb. Eventually, the read disturb can become so severe that the stored data becomes unreliable.
Prior art FIG. 3 is a graph 300 illustrating the effect of the phenomena called “data retention” on two of the four distributions. Data retention causes the distributions 222 and 224 to be shifted to the left as shown by distributions 322 and 324, which represent a negative voltage shift. Over time if the cell is not reprogrammed, the data retention shift can cause the stored data to become unreliable.
To widen the voltage margins, multi-level flash may operate at higher voltages than other memories. However, higher operating voltages cause other problems, such as oxide breakdown. Thus, alternative means of increasing margins are sought for this and other floating gate memories.
Thus, a need has arisen for a method of programming a multi-level cell memory array in a narrow distribution. An even further need exists for such a method that is efficient.